The present invention relates to data transfer between a rotary storage device and another storage device (e.g., between a magnetic disk and a disk cache). More particularly, the present invention pertains to simultaneous data transfer for a plurality of tracks between such storage devices.
Rotary storage devices, which are typically represented by magnetic disks, are suitable for storing a large amount of data but disadvantageously involve a long access time and a low data transfer rate. A disk cache subsystem such as that disclosed in U.S. Pat. No. 3,569,938 is one means for overcoming the above-described disadvantages of the rotary storage devices. However, when data transfer is between a disk cache and a disk, there is still room for improvement insofar as the mechanism for transferring data is concerned.
FIG. 1 shows one example of disk cache subsystems. Disk control units (DKC's) 101 and 102 are connected to the same CPU or different CPU's through channel interfaces 111 and 112, respectively. A cache memory 121 is shared by the DKC's 101 and 102. N disk drive units (DKU's) 141a to 141n are connected to the DKC's 101 and 102 through device interfaces 131 and 132, respectively.
When the DKC 101 (or 102) receives a data read request directed to one of the DKU's (e.g., DKU #i) through the channel interface 111 (or 112), the DKC 101 (or 102) searches the cache memory 121. If the requested data is present in the cache memory 121, that is, if a read-hit occurs, the data is transferred from the cache memory 121 to the CPU, and no access to the DKU #i is effected. On the other hand, if the requested data is not present in the cache memory 121, that is, if a read-miss occurs, the DKC 101 (or 102) establishes connection to the DKU #i through the device interface 131 (or 132), reads out the requested data from the DKU #i and sends it to the CPU.
When a read-miss occurs, that is, when required data is read out from a disk, a considerably long time is consumed in seeking for the track and waiting for the disk rotation. In addition to that, since the data transfer rate is limited by the rotational speed of the disk, the time required to respond to a data read request is undesirably extended. On the other hand, when a read-hit occurs, that is, when data transfer is effected from the cache memory, there is no such latency time nor restriction on the data transfer rate, and therefore the response time is favorably short. Accordingly, it is important to enhance the probability of a read-hit occurring. For this purpose, an operation which is known as preloading is generally carried out. In preloading, when a disk is accessed due to an occurrence of a read-miss, data stored on a track including the requested data and data on the following several tracks are pre-loaded into the cache memory. This measure is taken on the basis of the statistical fact that there is a strong probability that data which is in the vicinity of data which has once been accessed will be accessed in the near future.
However, during preloading, the DKC and DKU which are involved therein are kept connected with each other, which means that this DKC cannot respond for another service request. In a store-in type cache memory, the same problem arises also when the contents of a certain block in the cache memory are transferred to a disk for swapping. The time required for data transfer in such cases is desired to be as short as possible.
Generally speaking, it may be obvious that the time required for data transfer is shortened by effecting data transfer for a plurality of tracks in parallel. Japanese Pat. Laid-Open No. 108915/1980 discloses one type of mechanism in which the time required for reading and writing data is shortened by carrying out data transfer for a plurality of tracks in parallel. However, this mechanism is arranged such that a plurality of bits which constitute each character are written and read in parallel by means of a plurality of heads, which means that this mechanism cannot be employed to transfer independent data on different tracks. It is general practice to adopt the variable length recording system for magnetic disks. In this system, data on different tracks are respectively made up of records having different lengths, and each record has a specific field for storing data which indicates the length of the record. Further, if the recording surface has any defect, the data which is written therein is kept away from the defect. The position of such defects usually differs from track to track. Therefore, the reading and writing of this type of data requires a considerably complicated control, and such a control is generally carried out by a processor in a DKC. Accordingly, if parallel data transfer for a plurality of tracks is implemented in a straight forward manner, it is necessary to provide as many processors as the number of tracks which are handled in parallel.